Many electronic systems, such as memory devices, use a clock generating circuit that generates an internal clock signal that is phase aligned to an external clock signal. The phase alignment is necessary so that data can be exchanged reliably between the electronic systems and external devices.
A phase locked loop (PLL) is a clock generating circuit that is often used to generate an internal clock signal that is aligned to an external clock signal. FIG. 1 is a functional block diagram of a conventional phase locked loop (PLL) 100. The PLL 100 includes a voltage controlled oscillator (VCO) 104 that receives a VCO control (VCTRL) signal and generates a VCO clock (VCOCLK) signal. The PLL 100 also includes a phase frequency detector (PFD) 108 coupled to the VCO 104. The PFD 108 compares the phase of the VCOCLK signal to the phase of the reference clock (RCLK) signal to generate an UP and a DN signal depending on the relative phases of the VCOCLK and RCLK signals.
The PLL 100 also includes a VCO control circuit 112 coupled to the PFD 108. The VCO control circuit 112 receives the UP and DN signals, and generates the VCTRL signal. The VCTRL signal is a phase error signal having a magnitude that increases responsive to the UP signal and decreases responsive to the DN signal.
FIGS. 2(a) and 2(b) are example signal timing diagrams illustrating various signals generated during operation of the PLL 100 of FIG. 1. In the example of FIG. 2(a) the VCOCLK signal leads the RCLK signal, and in response to a rising edge of the VCOCLK signal, the PFD 108 drives the DN signal high. The DN signal remains high until the PFD 108 receives the next rising edge of the RCLK signal. In FIG. 2(a) the UP signal always remains low because the RCLK signal never leads the VCOCLK signal. When the DN signal is high, the VCTRL signal decreases, which adjusts the VCOCLK signal so that the phase of the VCOCLK signal is aligned to the phase of the RCLK signal.
In the example of FIG. 2(b), the RCLK signal leads the VCOCLK signal. In response to a rising edge of the RCLK signal, the PFD 108 drives the UP signal high. The UP signal remains high until the PFD 108 receives the next rising edge of the VCOCLK signal. The DN signal always remains low because the VCOCLK signal never leads the RCLK signal. As shown in FIG. 2(b), when the UP signal is high, the VCTRL signal increases, which adjusts the VCOCLK signal until it is aligned with the RCLK signal.
When the PLL 100 is initially powered, the frequency of the VCOCLK signal may be different from the frequency of the RCLK signal. The UP and DN signals cause the frequency of the VCOCLK signal to be gradually pulled toward the frequency of the RCLK signal. If the frequency of the VCOCLK signal is less than the frequency of the RCLK signal, the UP signal causes the frequency of the VCOCLK signal to increase until the frequencies of the VCOCLK and RCLK signals are closely matched. If the frequency of the VCOCLK signal is greater than the frequency of the RCLK signal, the DN signal causes the frequency of the VCOCLK signal to decrease until the frequencies of the VCOCLK and RCLK signals are closely matched. When the frequency of the VCOCLK signal is closely matched to the frequency of the RCLK signal, the PLL 100 is considered “locked.” The VCTRL signal is then used to adjust the phase of the VCOCLK signal until the VCOCLK and RCLK signals are phase aligned. However, it can require a considerable period of time for the PLL 100 to achieve a locked condition.
A delay locked loop (DLL) is also used as a clock generating circuit to align an external clock signal to an internal clock signal. FIG. 3 is a functional block diagram of a conventional DLL 300. The DLL 300 includes a variable delay line (VDL) 304 that receives an external clock (RCLK) signal and generates a delayed clock (DELCLK) signal in response to the RCLK signal. The DLL 300 further includes a phase detector 308 that receives the RCLK and DELCLK signals and generates an UP and a DN signal. The respective values of the UP and DN signals depend on the phase difference between the RCLK and DELCLK signals.
If the DELCLK signal lags the RCLK signal by less than one cycle, the DN signal goes high and remains high until the next rising edge of the RCLK signal. When the DELCLK signal lags the RCLK signal by less than one cycle, the UP signal remains low.
If the DELCLK signal lags the RCLK signal by more than one cycle, the UP signal goes high and remains high until the next rising edge of the DELCLK signal. When the DELCLK signal lags the RCLK signal by more than one cycle, the DN signal remains low.
A delay controller 312 generates a DADJ signal in response to the UP and DN signals from the phase detector 308. The delay controller 312 applies the DADJ signal to the VDL 304 to adjust the variable delay of the VDL 304. The phase detector 308 and the delay controller 312 operate in combination to adjust the variable delay of the VDL 304 as a function of the detected phase between the RCLK and DELCLK signals until the phase difference between the RCLK and DELCLK signals is approximately zero.
FIGS. 4(a) and 4(b) are signal timing diagrams illustrating various signals generated during operation of the DLL 300 of FIG. 3. In FIG. 4(a) the DELCLK signal lags the RCLK signal by less than one cycle. In response to a rising edge of the DELCLK signal, the PD 308 drives the DN signal high where it remains until the next rising edge of the RCLK signal In FIG. 4(a) the UP signal always remains low because the RCLK signal never leads the DELCLK signal.
In FIG. 4(b) the DELCLK signal lags the RCLK signal by more than one cycle. In response to a rising edge of the RCLK signal, the PD 308 drives the UP signal high where it remains until the next rising edge of the DELCLK signal. In FIG. 4(b) the DN signal always remains low because the VCOCLK never leads the RCLK signal.
As discussed before with reference to FIGS. 4(a) and 4(b), the DLL 300 adjusts only the phase of the DELCLK signal. Thus, the DLL 300 typically provides faster lock than the PLL 100 because the PLL 100 must initially adjust the frequency of the VCOCLK signal. However, since the DLL 300 uses the RCLK signal to generate the DELCLK signal, any jitter present in the RCLK signal will be present in the DELCLK signal. Thus, the DLL 300 is typically used when there is a relatively clean (i.e., less jittery) RCLK signal or jitter can be tolerated.
Accordingly, there is a need for a clock generating circuit that allows an internal clock signal to be quickly aligned to an external clock signal, and which is not susceptible to high frequency jitters in the external clock signal.